ASM811, ASM812
October 2003
rev 1.0
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MR Glitch Immunity
Note 3
100
ns
MR to RESET Propogation
Delay
tMD
Note 2
0.5
µs
V
VIH
VIL
VIH
VIL
2.3
0.77VCC
10
VCC > VTH (MAX),
ASM811/812L/M/J
MR Input Threshold
0.8
VCC > VTH (MAX),
ASM811/812R/S/T
MR Input Threshold
V
0.25VCC
MR Pullup Resistance
20
30
kΩ
V
CC= VTH min., ISINK = 1.2mA,
ASM811R/S/T
0.3
Low RESET Output Voltage
(ASM811)
VOL
VCC= VTH min., ISINK = 3.2mA,
ASM811L/M/J
0.4
0.3
V
V
CC > 1.1V, ISINK = 50µA
V
V
CC > VTH max., ISOURCE = 500µA,
ASM811R/S/T
0.8VCC
High RESET Output Voltage
(ASM811)
VOH
V
V
CC > VTH max., ISOURCE = 800µA,
ASM811L/M/J
VCC - 1.5
V
CC= VTH max., ISINK = 1.2mA,
ASM812R/S/T
Low RESET Output Voltage
(ASM812)
VOL
0.3
0.4
V
CC= VTH max., ISINK = 3.2mA,
ASM812L/M/J
High RESET Output Voltage
(ASM812)
VOH
TRST
1.8V < VCC < VTH min., ISOURCE = 150µA
VCC > VTH
0.8VCC
140
V
Active Reset Timeout Period
240
180
msec
msec
Manual Active Reset Time-
out Period
TMRST
MR returns HIGH
Notes:
1. Production testing done at TA = 25°C. Over-temperature specifications guaranteed by design only using six sigma design limits.
2. RESET output is active LOW for the ASM811 and RESET output is active HIGH for the ASM812.
3. Glitches of 100ns or less typically will not generate a reset pulse.
6 of 10
4 Pin µP Voltage Supervisor with Manual Reset
Notice: The information in this document is subject to change without notice
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
