November 2005
rev 1.7
Notebook LCD Panel EMI Reduction IC
Features
FCC approved method of EMI attenuation.
Provides up to 15dB EMI reduction.
Generates a low EMI Spread Spectrum clock and a
non-spread reference clock of the input frequency.
Optimized for Frequency range from 20 to 40MHz.
Internal loop filter minimizes external components
and board space.
Selectable spread options: Down and Center.
Low Inherent Cycle-to-Cycle jitter.
Eight spread % selections:
±0.625%
to –3.5%.
3.3V
±
0.3V Operating Voltage range.
Low power CMOS design.
Supports notebook VGA and other LCD timing
controller applications.
Power Down function for mobile application.
Available in Commercial temperature range.
Available in 8-pin SOIC and TSSOP Packages.
P1819
ferrite beads, shielding and other passive components that
are traditionally required to pass EMI regulations.
The P1819 modulates the output of a single PLL in order to
“spread” the bandwidth of a synthesized clock, and more
importantly,
decreases
the
peak
amplitudes
of
its
harmonics. This results in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most frequency generators. Lowering EMI
by increasing a signal’s bandwidth is called ‘Spread
Spectrum Clock Generation’.
The P1819 uses the most efficient and optimized
modulation
profile
approved
by
the
FCC
and
is
implemented in a proprietary all digital method.
Applications
The P1819 is targeted towards EMI management for
memory and LVDS interfaces in mobile graphic chipsets
and high-speed digital applications such as PC peripheral
devices, consumer electronics, and embedded controller
systems.
Product Description
The P1819 is a Versatile Spread Spectrum Frequency
Modulator designed specifically for input clock frequencies
from 20 to 40MHz. (Refer
Input Frequency and Modulation
Rate
Table).
The
P1819
reduces
electromagnetic
interference (EMI) at the clock source, allowing system
wide reduction of EMI of
down stream clock and data
dependent signals. The P1819 allows significant system
cost savings by reducing the number of circuit board layers
Block Diagram
D_C/NC PD# SRS
VDD
Modulation
XIN/CLKIN
Crystal
Oscillator
XOUT
Frequenc
y
Feedback
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
REF
ModOUT
VSS
Alliance Semiconductor
2575 Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
