a6850
®
Asynchronous Communications
Interface Adapter
Data Sheet
September 1996, ver. 1
Features
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a6850
MegaCore function implementing an asychronous
communications interface adapter (ACIA)
Optimized for FLEX
®
and MAX
®
architectures
Programmable word lengths, stop bits, and parity
Offers divide-by-1, -16, or -64 mode
Includes error detection
Uses approximately 237 FLEX logic elements (LEs)
Functionally based on the Motorola MC6850 device, except as noted
in the
“Variations & Clarifications” section on page 94
General
Description
The
a6850
MegaCore function implements an ACIA, which is a universal
asynchronous receiver/transmitter (UART). The
a6850
provides an
interface between a microprocessor and a serial communications channel.
The
a6850
receives and transmits data in a variety of configurations,
including 7- or 8-bit data words, with odd, even, or no parity, and 1 or 2
stop bits. See
Figure 1.
Figure 1. a6850 Symbol
A6850
nCTS
nDCD
E
nRESET
RS
RnW
RXCLK
RXDATA
TXCLK
CS[2..0]
DI[7..0]
nIRQ
nRTS
TXDATA
DO[7..0]
Altera Corporation
A-DS-A6850-01
81
ALTERA [ ALTERA CORPORATION ]
