Cyclone Device Handbook, Volume 1
Figure 2–5. Cyclone LE
Register chain
routing from
previous LE
LAB-wide
Synchronous
Load
Register Bypass
Packed
LAB Carry-In
Programmable
Register
LAB-wide
Carry-In1
addnsub
Synchronous
Clear
Register Select
Carry-In0
LUT chain
routing to next LE
data1
Row, column,
and direct link
routing
PRN/ALD
data2
data3
Synchronous
Load and
Clear Logic
Look-Up
Table
(LUT)
Carry
Chain
D
Q
ADATA
data4
ENA
CLRN
Row, column,
and direct link
routing
labclr1
labclr2
Asynchronous
Clear/Preset/
Load Logic
Local Routing
labpre/aload
Chip-Wide
Reset
Register chain
output
Clock &
Clock Enable
Select
Register
Feedback
labclk1
labclk2
labclkena1
labclkena2
Carry-Out0
Carry-Out1
LAB Carry-Out
Each LE's programmable register can be configured for D, T, JK, or SR
operation. Each register has data, true asynchronous load data, clock,
clock enable, clear, and asynchronous load/preset inputs. Global signals,
general-purpose I/O pins, or any internal logic can drive the register's
clock and clear control signals. Either general-purpose I/O pins or
internal logic can drive the clock enable, preset, asynchronous load, and
asynchronous data. The asynchronous load data input comes from the
data3input of the LE. For combinatorial functions, the LUT output
bypasses the register and drives directly to the LE outputs.
Each LE has three outputs that drive the local, row, and column routing
resources. The LUT or register output can drive these three outputs
independently. Two LE outputs drive column or row and direct link
routing connections and one drives local interconnect resources. This
allows the LUT to drive one output while the register drives another
output. This feature, called register packing, improves device utilization
because the device can use the register and the LUT for unrelated
2–6
Preliminary
Altera Corporation
January 2007
ALTERA [ ALTERA CORPORATION ]
