Preliminary Information
Cyclone FPGA Family Data Sheet
The smallest unit of logic in the Cyclone architecture, the LE, is compact
and provides advanced features with efficient logic utilization. Each LE
contains a four-input LUT, which is a function generator that can
implement any function of four variables. In addition, each LE contains a
programmable register and carry chain with carry select capability. A
single LE also supports dynamic single bit addition or subtraction mode
selectable by an LAB-wide control signal. Each LE drives all types of
interconnects: local, row, column, LUT chain, register chain, and direct
link interconnects. See Figure 5.
Logic Elements
Figure 5. Cyclone LE
Register chain
routing from
previous LE
LAB-wide
Synchronous
Register Bypass
LAB Carry-In
Load
Programmable
Register
LAB-wide
Synchronous
Clear
Packed
Register Select
Carry-In1
Carry-In0
addnsub
LUT chain
routing to next LE
data1
Row, column,
and direct link
routing
PRN/ALD
data2
data3
Synchronous
Load and
Clear Logic
Look-Up
Table
(LUT)
Carry
Chain
D
Q
ADATA
data4
ENA
CLRN
Row, column,
and direct link
routing
labclr1
labclr2
Asynchronous
Clear/Preset/
Load Logic
Local Routing
labpre/aload
Chip-Wide
Reset
Register chain
output
Clock &
Clock Enable
Select
Register
Feedback
labclk1
labclk2
labclkena1
labclkena2
Carry-Out0
Carry-Out1
LAB Carry-Out
Altera Corporation
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ALTERA [ ALTERA CORPORATION ]
