Preliminary Information
Cyclone FPGA Family Data Sheet
Dynamic Arithmetic Mode
The dynamic arithmetic mode is ideal for implementing adders, counters,
accumulators, wide parity functions, and comparators. An LE in dynamic
arithmetic mode uses four 2-input LUTs configurable as a dynamic
adder/subtractor. The first two 2-input LUTs compute two summations
based on a possible carry-in of 1 or 0; the other two LUTs generate carry
outputs for the two chains of the carry select circuitry. As shown in
Figure 7,
the LAB carry-in signal selects either the
carry-in0
or
carry-in1
chain. The selected chain’s logic level in turn determines
which parallel sum is generated as a combinatorial or registered output.
For example, when implementing an adder, the sum output is the
selection of two possible calculated sums:
data1 + data2 + carry-in0
or
data1 + data2 + carry-in1.
The other two LUTs use the
data1
and
data2
signals to generate two
possible carry-out signalsone for a carry of 1 and the other for a carry of
0. The
carry-in0
signal acts as the carry select for the
carry-out0
output and
carry-in1
acts as the carry select for the
carry-out1
output. LEs in arithmetic mode can drive out registered and unregistered
versions of the LUT output.
The dynamic arithmetic mode also offers clock enable, counter enable,
synchronous up/down control, synchronous clear, synchronous load,
and dynamic adder/subtractor options. The LAB local interconnect data
inputs generate the counter enable and synchronous up/down control
signals. The synchronous clear and synchronous load options are LAB-
wide signals that affect all registers in the LAB. The Quartus II software
automatically places any registers that are not used by the counter into
other LABs. The
addnsub
LAB-wide signal controls whether the LE acts
as an adder or subtractor.
Altera Corporation
13
ALTERA [ ALTERA CORPORATION ]
