I/O Structure
Figure 2–71. LVDS Input Differential On-Chip Termination
Transmitting
Device
Receiving Device with
Differential Termination
Z
Z
0
+
+
R
D
Ð
Ð
0
I/O banks on the left and right side of the device support LVDS receiver
(far-end) differential termination.
Table 2–33 shows the Stratix device differential termination support.
Table 2–33. Differential Termination Supported by I/O Banks
Top & Bottom
Banks (3, 4, 7 & 8)
Left & Right Banks
(1, 2, 5 & 6)
Differential Termination Support
I/O Standard Support
Differential termination (1), (2)
LVDS
v
Notes to Table 2–33:
(1) Clock pin CLK0, CLK2, CLK9, CLK11, and pins FPLL[7..10]CLKdo not support differential termination.
(2) Differential termination is only supported for LVDS because of a 3.3-V VCC IO
.
Table 2–34 shows the termination support for different pin types.
Table 2–34. Differential Termination Support Across Pin Types
RD
Pin Type
Top and bottom I/O banks (3, 4, 7, and 8)
DIFFIO_RX[]
v
v
CLK[0,2,9,11],CLK[4-7],CLK[12-15]
CLK[1,3,8,10]
FCLK
FPLL[7..10]CLK
The differential on-chip resistance at the receiver input buffer is
118 Ω 20 %.
2–128
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
ALTERA [ ALTERA CORPORATION ]
