PLLs & Clock Networks
resynchronization or relock period. The
clkena
signal can also disable
clock outputs if the system is not tolerant to frequency overshoot during
resynchronization.
The
extclkena
signals work in the same way as the
clkena
signals, but
they control the external clock output counters (e0,
e1, e2,
and
e3).
Upon
re-enabling, the PLL does not need a resynchronization or relock period
unless the PLL is using external feedback mode. In order to lock in
external feedback mode, the external output must drive the board trace
back to the
FBIN
pin.
Figure 2–57. extclkena Signals
COUNTER
OUTPUT
CLKENA
CLKOUT
Fast PLLs
Stratix devices contain up to eight fast PLLs with high-speed serial
interfacing ability, along with general-purpose features.
shows a diagram of the fast PLL.
2–100
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
ALTERA [ ALTERA CORPORATION ]
