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EP1S30F1508I6ES 参数 Datasheet PDF下载

EP1S30F1508I6ES图片预览
型号: EP1S30F1508I6ES
PDF下载: 下载PDF文件 查看货源
内容描述: Stratix器件系列数据手册 [Stratix Device Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑LTE
文件页数/大小: 290 页 / 3583 K
品牌: ALTERA [ ALTERA CORPORATION ]
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3. Configuration & Testing
S51003-1.3
IEEE Std. 1149.1
(JTAG)
Boundary-Scan
Support
All Stratix
®
devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan testing can be
performed either before or after, but not during configuration. Stratix
devices can also use the JTAG port for configuration together with either
the Quartus
®
II software or hardware using either Jam Files (.jam) or Jam
Byte-Code Files (.jbc).
Stratix devices support IOE I/O standard setting reconfiguration through
the JTAG BST chain. The JTAG chain can update the I/O standard for all
input and output pins any time before or during user mode through the
CONFIG_IO
instruction. You can use this ability for JTAG testing before
configuration when some of the Stratix pins drive or receive from other
devices on the board using voltage-referenced standards. Since the Stratix
device may not be configured before JTAG testing, the I/O pins may not
be configured for appropriate electrical standards for chip-to-chip
communication. Programming those I/O standards via JTAG allows you
to fully test the I/O connection to other devices.
The enhanced PLL reconfiguration bits are part of the JTAG chain before
configuration and after power-up. After device configuration, the PLL
reconfiguration bits are not part of the JTAG chain.
The JTAG pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O standards. The
TDO
pin voltage is determined by the V
CCIO
of the bank where it resides.
The
VCCSEL
pin selects whether the JTAG inputs are 1.5-V, 1.8-V, 2.5-V, or
3.3-V compatible.
Stratix devices also use the JTAG port to monitor the logic operation of the
device with the SignalTap
®
II embedded logic analyzer. Stratix devices
support the JTAG instructions shown in
The Quartus II software has an Auto Usercode feature where you can
choose to use the checksum value of a programming file as the JTAG user
code. If selected, the checksum is automatically loaded to the
USERCODE
register. In the Settings dialog box in the Assignments menu, click
Device
& Pin Options,
then
General,
and then turn on the
Auto Usercode
option.
Altera Corporation
July 2005
3–1