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EP1S40B1508I7ES 参数 Datasheet PDF下载

EP1S40B1508I7ES图片预览
型号: EP1S40B1508I7ES
PDF下载: 下载PDF文件 查看货源
内容描述: Stratix器件系列数据手册 [Stratix Device Family Data Sheet]
分类和应用:
文件页数/大小: 290 页 / 3583 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Digital Signal Processing Block
Output Selection Multiplexer
The outputs from the various elements of the adder/output block are
routed through an output selection multiplexer. Based on the DSP block
operational mode and user settings, the multiplexer selects whether the
output from the multiplier, the adder/subtractor/accumulator, or
summation block feeds to the output.
Output Registers
Optional output registers for the DSP block outputs are controlled by four
sets of control signals:
clock[3..0], aclr[3..0],
and
ena[3..0].
Output registers can be used in any mode.
Modes of Operation
The adder, subtractor, and accumulate functions of a DSP block have four
modes of operation:
Simple multiplier
Multiply-accumulator
Two-multipliers adder
Four-multipliers adder
Each DSP block can only support one mode. Mixed modes in the
same DSP block is not supported.
1
Simple Multiplier Mode
In simple multiplier mode, the DSP block drives the multiplier sub-block
result directly to the output with or without an output register. Up to four
18 × 18-bit multipliers or eight 9 × 9-bit multipliers can drive their results
directly out of one DSP block. See
2–64
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005