DC & Switching Characteristics
Table 4–124 provides high-speed timing specifications definitions.
High-Speed I/O
Specification
Table 4–124. High-Speed Timing Specifications & Terminology
High-Speed Timing Specification
Terminology
tC
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Low-to-high transmission time.
fHSCLK
tRISE
tFALL
High-to-low transmission time.
Timing unit interval (TUI)
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = tC/w).
fHSDR
Maximum LVDS data transfer rate (fHSDR = 1/TUI).
Channel-to-channel skew (TCCS)
The timing difference between the fastest and slowest output edges,
including tCO variation and clock skew. The clock is included in the TCCS
measurement.
Sampling window (SW)
The period of time during which the data must be valid to be captured
correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
SW = tSW (max) – tSW (min).
Input jitter (peak-to-peak)
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
Deserialization factor (width of internal data bus).
PLL multiplication factor.
Output jitter (peak-to-peak)
tDUTY
tLOCK
J
W
Altera Corporation
July 2005
4–87
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
