DLL Jitter
Table 4–133. Fast PLL Specifications for -8 Speed Grades (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
tARESET
10
ns
Minimum pulse width on areset
signal
Notes to Tables 4–131 through 4–133:
(1) See “Maximum Input & Output Clock Rates” on page 4–76.
(2) PLLs 7, 8, 9, and 10 in the EP1S80 device support up to 717-MHz input and output.
(3) Use this equation (fOU T = fIN * ml(n × post-scale counter)) in conjunction with the specified fINPFD and fV CO
ranges to determine the allowed PLL settings.
(4) When using the SERDES, high-speed differential I/O mode supports a maximum output frequency of 210 MHz
to the global or regional clocks (that is, the maximum data rate 840 Mbps divided by the smallest SERDES J factor
of 4).
(5) Refer to the section “High-Speed I/O Specification” on page 4–87 for more information.
(6) This parameter is for high-speed differential I/O mode only.
(7) These counters have a maximum of 32 if programmed for 50/50 duty cycle. Otherwise, they have a maximum
of 16.
(8) High-speed differential I/O mode supports W = 1 to 16 and J = 4, 7, 8, or 10.
Table 4–134 reports the jitter for the DLL in the DQS phase shift reference
circuit.
DLL Jitter
Table 4–134. DLL Jitter for DQS Phase Shift Reference Circuit
Frequency (MHz)
DLL Jitter (ps)
197 to 200
160 to 196
100 to 159
100
300
500
f
For more information on DLL jitter, see the DDR SRAM section in the
Stratix Architecture chapter of the Stratix Device Handbook, Volume 1.
4–102
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
ALTERA [ ALTERA CORPORATION ]
