Digital Signal Processing Block
For FIR filters, the DSP block combines the four-multipliers adder mode
with the shift register inputs. One set of shift inputs contains the filter
data, while the other holds the coefficients loaded in serial or parallel. The
input shift register eliminates the need for shift registers external to the
DSP block (i.e., implemented in LEs). This architecture simplifies filter
design since the DSP block implements all of the filter circuitry.
One DSP block can implement an entire 18-bit FIR filter with up to four
taps. For FIR filters larger than four taps, DSP blocks can be cascaded with
additional adder stages implemented in LEs.
Table 2–16 shows the different number of multipliers possible in each
DSP block mode according to size. These modes allow the DSP blocks to
implement numerous applications for DSP including FFTs, complex FIR,
FIR, and 2D FIR filters, equalizers, IIR, correlators, matrix multiplication
and many other functions.
Table 2–16. Multiplier Size & Configurations per DSP block
DSP Block Mode
9 × 9
18 × 18
36 × 36 (1)
Multiplier
Eight multipliers with
eight product outputs
Four multipliers with four One multiplier with one
product outputs
product output
Multiply-accumulator
Two-multipliers adder
Four-multipliers adder
Two multiply and
accumulate (52 bits)
Two multiply and
accumulate (52 bits)
–
Four sums of two
Two sums of two
–
–
multiplier products each multiplier products each
Two sums of four One sum of four multiplier
multiplier products each products each
Note to Table 2–16:
(1) The number of supported multiply functions shown is based on signed/signed or unsigned/unsigned
implementations.
DSP Block Interface
Stratix device DSP block outputs can cascade down within the same DSP
block column. Dedicated connections between DSP blocks provide fast
connections between the shift register inputs to cascade the shift register
chains. You can cascade DSP blocks for 9 × 9- or 18 × 18-bit FIR filters
larger than four taps, with additional adder stages implemented in LEs.
If the DSP block is configured as 36 × 36 bits, the adder, subtractor, or
accumulator stages are implemented in LEs. Each DSP block can route
the shift register chain out of the block to cascade two full columns of DSP
blocks.
2–70
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
