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EP20K600C 参数 Datasheet PDF下载

EP20K600C图片预览
型号: EP20K600C
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程逻辑 [Programmable Logic]
分类和应用: 可编程逻辑
文件页数/大小: 90 页 / 594 K
品牌: ALTERA [ ALTERA CORPORATION ]
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APEX 20KC
®
Programmable Logic
Device
Data Sheet
February 2004 ver. 2.2
Features...
Programmable logic device (PLD) manufactured using a 0.15-µm all-
layer copper-metal fabrication process
25 to 35% faster design performance than APEX
TM
20KE devices
Pin-compatible with APEX 20KE devices
High-performance, low-power copper interconnect
MultiCore
TM
architecture integrating look-up table (LUT) logic
and embedded memory
LUT logic used for register-intensive functions
Embedded system blocks (ESBs) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
High-density architecture
200,000 to 1 million typical gates (see
Table 1)
Up to 38,400 logic elements (LEs)
Up to 327,680 RAM bits that can be used without reducing
available logic
Note (1)
EP20K400C
1,052,000
400,000
16,640
104
212,992
4
-7, -8, -9
1,664
488
Table 1. APEX 20KC Device Features
Feature
Maximum system gates
Typical gates
LEs
ESBs
Maximum RAM bits
PLLs
(2)
Speed grades
(3)
Maximum macrocells
Maximum user I/O pins
Notes to
Table 1:
(1)
(2)
(3)
EP20K200C
526,000
200,000
8,320
52
106,496
2
-7, -8, -9
832
376
EP20K600C
1,537,000
600,000
24,320
152
311,296
4
-7, -8, -9
2,432
588
EP20K1000C
1,772,000
1,000,000
38,400
160
327,680
4
-7, -8, -9
2,560
708
The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to
57,000 additional gates.
PLL: phase-locked loop.
The -7 speed grade provides the fastest performance.
Altera Corporation
DS-APEX20KC-2.2
1