Classic
®
EPLD Family
Data Sheet
May 1999, ver. 5
Features
s
s
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s
s
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Complete device family with logic densities of 300 to 900 usable gates
(see
Table 1)
Device erasure and reprogramming with non-volatile EPROM
configuration elements
Fast pin-to-pin logic delays as low as 10 ns and counter frequencies
as high as 100 MHz
24 to 68 pins available in dual in-line package (DIP), plastic J-lead
chip carrier (PLCC), pin-grid array (PGA), and small-outline
integrated circuit (SOIC) packages
Programmable security bit for protection of proprietary designs
100% generically tested to provide 100% programming yield
Programmable registers providing D, T, JK, and SR flipflops with
individual clear and clock controls
Software design support featuring the Altera
®
MAX+PLUS
®
II
development system on Windows-based PCs, as well as
Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000
workstations, and third-party development systems
Programming support with Altera’s Master Programming Unit
(MPU); programming hardware from Data I/O, BP Microsystems,
and other third-party programming vendors
Additional design entry and simulation support provided by EDIF,
library of parameterized modules (LPM), Verilog HDL, VHDL, and
other interfaces to popular EDA tools from manufacturers such as
Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
Synplicity, and VeriBest
Table 1. Classic Device Features
Feature
Usable gates
Macrocells
Maximum user I/O pins
t
PD
(ns)
f
CNT
(MHz)
EP610
EP610I
300
16
22
10
100
EP910
EP910I
450
24
38
12
76.9
EP1810
900
48
64
20
50
Altera Corporation
A-DS-CLASSIC-05
745
ALTERA [ ALTERA CORPORATION ]
