2. Enhanced Configuration
Devices (EPC4, EPC8 &
EPC16) Data Sheet
CF52002-2.1
Features
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Enhanced configuration devices include EPC4, EPC8, and EPC16
devices
Single-chip configuration solution for Stratix
®
series, Cyclone™
series, APEX™ II, APEX 20K (including APEX 20K, APEX 20KC, and
APEX 20KE), Mercury™, ACEX
®
1K, and FLEX
®
10K (FLEX 10KE
and FLEX 10KA) devices
Contains 4-, 8-, and 16-Mbit flash memories for configuration data
storage
On-chip decompression feature almost doubles the effective
●
configuration density
Standard flash die and a controller die combined into single stacked
chip package
External flash interface supports parallel programming of flash and
external processor access to unused portions of memory
●
Flash memory block/sector protection capability via external
flash interface
●
Supported in EPC16 and EPC4 devices
Page mode support for remote and local reconfiguration with up to
eight configurations for the entire system
Compatible with Stratix series Remote System Configuration
●
feature
Supports byte-wide configuration mode fast passive parallel (FPP);
8-bit data output per
DCLK
cycle
Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of
Altera FPGAs
Pin-selectable 2-ms or 100-ms power-on reset (POR) time
Configuration clock supports programmable input source and
frequency synthesis
●
Multiple configuration clock sources supported (internal
oscillator and external clock input pin)
●
External clock source with frequencies up to 133 MHz
Internal oscillator defaults to 10 MHz; Programmable for higher
●
frequencies of 33, 50, and 66 MHz
Clock synthesis supported via user programmable divide
●
counter
Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin
Ultra FineLine BGA
®
packages
Vertical migration between all devices supported in the 100-pin
●
PQFP package
Supply voltage of 3.3 V (core and I/O)
Altera Corporation
August 2005
2–1
ALTERA [ ALTERA CORPORATION ]
