欢迎访问ic37.com |
会员登录 免费注册
发布采购

EPM2210 参数 Datasheet PDF下载

EPM2210图片预览
型号: EPM2210
PDF下载: 下载PDF文件 查看货源
内容描述: JTAG和在系统可编程 [JTAG & In-System Programmability]
分类和应用:
文件页数/大小: 10 页 / 104 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EPM2210的Datasheet PDF文件第2页浏览型号EPM2210的Datasheet PDF文件第3页浏览型号EPM2210的Datasheet PDF文件第4页浏览型号EPM2210的Datasheet PDF文件第5页浏览型号EPM2210的Datasheet PDF文件第6页浏览型号EPM2210的Datasheet PDF文件第7页浏览型号EPM2210的Datasheet PDF文件第8页浏览型号EPM2210的Datasheet PDF文件第9页  
Chapter 3. JTAG & In-System
Programmability
MII51003-1.1
IEEE Std. 1149.1
(JTAG) Boundary
Scan Support
All MAX
®
II devices provide Joint Test Action Group (JTAG) boundary-
scan test (BST) circuitry that complies with the IEEE Std. 1149.1-2001
specification. JTAG boundary-scan testing can only be performed at any
time after V
CCINT
and all V
CCIO
banks have been fully powered and a
t
CONFIG
amount of time has passed. MAX II devices can also use the JTAG
port for in-system programming together with either the Quartus
®
II
software or hardware using Programming Object Files (.pof), Jam
TM
Standard Test and Programming Language (STAPL) Files (.jam) or Jam
Byte-Code Files (.jbc).
The JTAG pins support 1.5-V, 1.8-V, 2.5-V, or 3.3-V I/O standards. The
supported voltage level and standard is determined by the V
CCIO
of the
bank where it resides. The dedicated JTAG pins reside in Bank 1 of all
MAX II devices.
MAX II devices support the JTAG instructions shown in
Table 3–1. MAX II JTAG Instructions (Part 1 of 2)
JTAG Instruction
SAMPLE/PRELOAD
Instruction Code
00 0000 0101
Description
Allows a snapshot of signals at the device pins to be captured
and examined during normal device operation, and permits an
initial data pattern to be output at the device pins.
Allows the external circuitry and board-level interconnects to
be tested by forcing a test pattern at the output pins and
capturing test results at the input pins.
Places the 1-bit bypass register between the
TDI
and
TDO
pins, which allows the boundary scan test data to pass
synchronously through selected devices to adjacent devices
during normal device operation.
Selects the 32-bit
USERCODE
register and places it between
the
TDI
and
TDO
pins, allowing the
USERCODE
to be serially
shifted out of
TDO.
This register defaults to all 1’s if not
specified in the Quartus II software.
Selects the
IDCODE
register and places it between
TDI
and
TDO,
allowing the IDCODE to be serially shifted out of
TDO.
EXTEST
00 0000 1111
BYPASS
11 1111 1111
USERCODE
00 0000 0111
IDCODE
00 0000 0110
Altera Corporation
June 2004
Core Version a.b.c variable
3–1
Preliminary