欢迎访问ic37.com |
会员登录 免费注册
发布采购

EPM7128AETC144-7 参数 Datasheet PDF下载

EPM7128AETC144-7图片预览
型号: EPM7128AETC144-7
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程逻辑器件 [Programmable Logic Device]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 60 页 / 880 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EPM7128AETC144-7的Datasheet PDF文件第2页浏览型号EPM7128AETC144-7的Datasheet PDF文件第3页浏览型号EPM7128AETC144-7的Datasheet PDF文件第4页浏览型号EPM7128AETC144-7的Datasheet PDF文件第5页浏览型号EPM7128AETC144-7的Datasheet PDF文件第6页浏览型号EPM7128AETC144-7的Datasheet PDF文件第7页浏览型号EPM7128AETC144-7的Datasheet PDF文件第8页浏览型号EPM7128AETC144-7的Datasheet PDF文件第9页  
MAX 7000A
®
Includes
MAX 7000AE
Programmable Logic
Device
Data Sheet
October 2002, ver. 4.3
Features...
High-performance 3.3-V EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX
®
) architecture (see
Table 1)
3.3-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
MAX 7000AE device in-system programmability (ISP) circuitry
compliant with IEEE Std. 1532
EPM7128A and EPM7256A device ISP circuitry compatible with
IEEE Std. 1532
Built-in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1
Supports JEDEC Jam Standard Test and Programming Language
(STAPL) JESD-71
Enhanced ISP features
Enhanced ISP algorithm for faster programming (excluding
EPM7128A and EPM7256A devices)
ISP_Done bit to ensure complete programming (excluding
EPM7128A and EPM7256A devices)
Pull-up resistor on I/O pins during in-system programming
Pin-compatible with the popular 5.0-V MAX 7000S devices
High-density PLDs ranging from 600 to 10,000 usable gates
Extended temperature range
f
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V
MAX 7000B devices, see the
MAX 7000 Programmable Logic Device Family
Data Sheet
or the
MAX 7000B Programmable Logic Device Family Data Sheet.
Altera Corporation
DS-M7000A-4.3
1