HardCopy Series Handbook, Volume 1
Table 2–1. HardCopy II Family Overview (Part 2 of 2)
Feature
FPGA prototype
options
Notes to
(1)
HC210W devices use a wire bond package. All other HardCopy II devices and Stratix II FPGAs use a flip-chip
package. Devices in a wire bond package offer different performance and signal integrity characteristics compared
to devices in a flip-chip package.
This is the number of ASIC gates available in the HardCopy II base array for both logic and DSP functions that can
be implemented in a Stratix II FPGA prototype.
Total number of usable M4K blocks is 768, which allows migration compatibility when prototyping with an
EP2S180 device. This may be different from the Quartus II software total physical M4K count of the HC240.
The I/O pin counts include the dedicated clock input pins, which can be used for clock signals or data inputs.
The Quartus II I/O pin counts include an additional pin (PLLENA), which is not available as a general-purpose I/O
pin. The
PLLENA
pin can only be used to enable the PLLs.
HC210W
(1)
EP2S30
EP2S60
EP2S90
HC210
EP2S30
EP2S60
EP2S90
HC220
EP2S60
EP2S90
EP2S130
HC230
EP2S90
EP2S130
EP2S180
HC240
EP2S180
(2)
(3)
(4)
(5)
Functional
Description
The HardCopy II device family provides greater flexibility to design with
FPGA prototypes before moving to structured ASICs for production.
Before seamlessly migrating to the HardCopy II structured ASIC,
designers can prototype and test their design functionality using a
Stratix II FPGA. There are multiple options for the prototype FPGA,
allowing designers to choose the right HardCopy II device for volume
production and maximum cost savings. The Quartus II design software
includes features such as the Device Resource Guide, to help select the
optimal HardCopy II device based on the design requirements.
For more information on the Device Resource Guide, refer to the
Quartus II Support for HardCopy II Devices
chapter in the
HardCopy Series
Handbook.
HardCopy II devices require minimal involvement from the designer in
the device migration process. Additionally, unlike ASICs, the designer is
not required to generate test benches, test vectors, or timing and
functional simulations since prototyping is performed using an FPGA.
HardCopy II devices consist of base arrays that are common to all designs
for a particular device density, with design-specific customization done
using two metal layers. The reprogrammable FPGA logic, routing,
memory, and FPGA configuration-related logic are stripped from
HardCopy II devices. Removing all programmable and configuration
resources and replacing them with direct metal connections results in
considerable die size reduction and cost savings. A fine-grain architecture
consisting of an array of HCells extends the die reduction and cost
f
2–2
Preliminary
Altera Corporation
September 2008
ALTERA [ ALTERA CORPORATION ]
