Revision 1.27 - August 22, 2007
PPC405EZ – PowerPC 405EZ Embedded Processor
Preliminary Data Sheet
Table 15. I/O Specifications—All CPU Speeds (Sheet 2 of 2)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter
selected.
2. For all interfaces, I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
3. Maximum skew between IIC output signals is 6ns.
4. Maximum skew between all SPI output signals is 3ns. All SPI inputs signals are latched with less than 4ns of skew between
channels.
5. Maximum skew between all PWM output signals is 3.75ns. All PWM input signals are latched with less than 2.5ns of skew
between channels.
Input (ns)
Output (ns)
Output Current (mA)
Signal
ADC_InTrig
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(min)
I/O L
(min)
(TIS min)
(TIH min)
na
na
na
na
na
na
na
na
na
na
na
na
ADC_VRef
DAC_CRef
DAC_IOutP
DAC_IPTrig
DAC_IRRef
DAC_VRef
DAC_GRef
PWM_DivClk
PWM_OE[0]
PWM_OE[1:3]
PWM_TBA
PWM_1:15
IEEE_1588TS
Interrupts Interface
[IRQ0:4]
na
na
na
na
19.1
na
8.7
na
na
na
na
na
na
na
na
na
na
na
19.1
19.1
19.1
19.1
19.1
19.1
8.7
8.7
8.7
8.7
8.7
8.7
5
5
5
5
5
19.1
8.7
JTAG Interface
TCK
na
22.5
na
na
0
na
na
25
na
na
na
na
0
na
na
na
na
8.7
na
na
TDI
TCK
TCK
TCK
TCK
TDO
na
0
19.1
na
TMS
22.5
na
na
na
TRST
na
na
System Interface
GPIO000:31
GPIO100:20
Halt
na
na
na
na
0
na
na
na
15
na
na
na
na
na
na
19.1
19.1
na
8.7
8.7
na
22.5
na
na
TCK
TCK
SysErr
na
na
na
na
na
25.5
na
19.1
19.1
na
8.7
8.7
na
SysReset
TestEn
na
async
async
na
na
DebugEn
na
na
na
na
SysClk
na
na
na
na
AMCC Proprietary
49
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
