MEKONG
SONET/SDH STS-192/STM-64 MUX/DEMUX with Pointer Processor
Product Brief
Part Number S19204CBI12, Revision 1.21, June 2003
Features
• SONET/SDH Mux/Demux, Transport Overhead Terminating
Transceiver, & Pointer Processors for an STS-192/STM-64 and
up to 4 x STS-48/STM-16s.
• Provisionable as SONET or SDH on a per line basis.
• High Speed Side supports a 622 MHz 16-bit STS-192/STM-64
interface.
• Low Speed Side supports a 622 MHz 16-bit STS-192/STM-64
interface or four 622 MHz 4-bit STS-48/STM-16 interfaces.
• Cross-connects, in both directions, with STS-1 level granularity.
• Provisionable as SOH/LOH pass-through or termination/regen-
eration device.
• Compliant with ITU G.707, Bellcore GR-253, and ANSI T1.105
standards.
• STS-192/STM-64 framer.
• Non-Intrusive TOH Monitoring for all inputs: STS-192/STM-64
or 4x STS-48/STM-16.
• TOH can be either terminated/regenerated, or transparently
passed-through the device on a per function basis, in both
through-timing and pointer processing applications.
Demultiplex Direction
• Demultiplexes an STS-192/STM-64 into 4 STS-48/STM-16
connections or supports a bypass mode for STS-192/STM-64-
to-STS-192/STM-64 connections.
• Provisionable pointer processor bypass available for STS-192
to STS-192 operation (through-timing). Both a full bypass (no
frame regeneration) as well as a pointer processor bypass
(frame generation enabled) are provided.
• Selector for choosing demultiplexed tributaries from high-
speed interface, low-speed interfaces or from APS inputs.
• Non-Intrusive STS-192/STM-64 Frame and TOH Monitor.
• TOH can be either terminated/regenerated, or transparently
passed-through the device on a per function basis.
• STS-192/STM-64 or 4 x STS-48/STM-16 framer(s).
• Configurable TOH Generators for STS-192/STM-64 or STS-48/
STM-16 outputs.
Multiplex Direction
• Multiplexes 4 STS-48/STM-16 tributaries into an STS-192/
STM-64 or bypass for STS-192/STM-64-to-STS-192/STM-64
connections.
• Provisionable pointer processor bypass available for STS-192
to STS-192 operation (through-timing). Both a full bypass (no
frame regeneration) as well as a pointer processor bypass
(frame generation enabled) are provided.
• Selector for choosing high or low-speed interfaces, Deskew
Buffers, or APS inputs.
Figure 1: Block Diagram
MX_ALM[1:4]
MX_LOSEXT[1:4]
MX_TOH_LSDATA_OUT[1:4]
MX_TOH_LSSYNC_OUT[1:4]
MX_TOH_LSCLK_OUT[1:4]
MXPROTDATA_OUT_[1:4][3:0]
MX_PROT_CLK_OUT
MXPROTDATA_IN_[1:4][3:0]
MX_PROT_CLK_IN
MX_PROT_REFCLK_IN
MX_TOH_HSDATA_IN[3:0]
MX_TOH_HSFRM_OUT
MX_TOH_HSCLK_OUT
MX_TOH_HSEN
TOH
INSERT
MX_HSCLK_OUT
MX_HSDATA_OUT[15:0]
FRGN192
TOH
INSERT
RX FRMRS
MX_LSCLK_IN[1:4]
MX_LSDATA_IN[1:16]
or
MX_LSDATA_IN[1:4][3:0]
4xFR48 / FR192
TOH
DROP
MUX
16
TOH_Remap
PNTR
PROC./
DSKEW
POH
MON
DMUX
M
U
X
RSTB
INTB
D[15:0]
ADDR[13:0]
CSN
WRB(RWB)
RDYB(DTACKB)
BUSMODE
APS_INTB
UPCLK
MICROPROCESSOR I/F
4xFR48 / 1xFR192
TX FRAMGEN
Low Speed
Interface
DX_LSDATA_OUT[1:16]
or
DX_LSDATA_OUT[1:4][3:0]
DX_LSCLK_OUT[1:4]
Mux
Direction
FRAM192
MX_REFCLK_IN
SYS_REFCLK_OUT[1:4]
M
U
X
TOH_Remap
PNTR
PROC
X
High Speed
Interface
DX_HSCLK_IN
DX_HSDATA_IN[15:0]
TOH
INSERT
DX_TOH_LSDATA_IN[1:4]
DX_TOH_LSEN_IN[1:4]
DX_TOH_LSFRM_OUT[1:4]
DX_TOH_LSCLK_OUT[1:4]
FINAL / PRODUCTION RELASE Information
- The information contained in this
document is about a product in its fully tested and characterized stage. All fea-
tures described herein are dsupported. Contact AMCC for updates to this docu-
ment and the latest product status.
Empowering Intelligent Optical Networks
X
MUX
16
DX_PROT_REFCLK_IN
DX_PROT_CLK_IN
DX_PROT_DATA_IN_[1:4][3:0]
DX_PROT_CLK_OUT[1:4]
DX_PROT_DATA_OUT_[1:4][3:0]
DX_REFCLK_IN
DX_FRMSYNC_IN
POH
MON
Demux
Direction
TOH DROP
16
DX_ALARM_OUT
DX_LOSEXT
DX_TOH_HSDATA_OUT[3:0]
DX_TOH_HSFRM_OUT
DX_TOH_HSCLK_OUT
GPIO[15:0]
TDO
TCK
TMS
TDI
TRSTB
TS_EN
TEST_CLK
TEST_EN
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
