Revision 1.26 – April 25, 2007
440EP – PPC440EP Embedded Processor
Data Sheet
Table 6. Signal Functional Description (Sheet 2 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
DDR SDRAM Interface
BA0:1
Description
I/O
Type
Notes
Bank Address supporting up to four internal banks.
Selects up to four external DDR SDRAM banks.
Column Address Strobe.
O
O
O
O
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
BankSel0:3
CAS
ClkEn
Clock Enable.
DM0:3
DM8
Memory write data byte lane masks. DM8 is the byte lane
mask for the ECC byte lane.
O
2.5V SSTL_2
2.5V SSTL_2
DQS0:3
DQS8
Byte lane data strobe. DQS8 is the data strobe for the ECC
byte lane.
I/O
ECC0:7
ECC check bits 0:7.
Memory address bus.
I/O
O
2.5V SSTL_2
2.5V SSTL_2
MemAddr00:12
MemClkOut0
MemClkOut0
2.5V SSTL_2
Diff driver
Subsystem clock.
Memory data bus.
Self refresh.
O
I/O
I
MemData00:31
MemSelfRef
2.5V SSTL_2
3.3V tolerant
2.5V CMOS
5
RAS
Row Address Strobe.
Write Enable.
O
O
I
2.5V SSTL_2
2.5V SSTL_2
Volt ref receiver
WE
SVREF1
SSTL reference voltage.
Volt ref pin
(supplemental)
SVREF2A:B
Supplemental SSTL reference voltage.
I
AMCC Proprietary
51
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
