Revision 1.26 – April 25, 2007
440EP – PPC440EP Embedded Processor
Data Sheet
Table 17. I/O Specifications—333MHz to 533MHz
Notes:
1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.
Input (ns)
Signal
Setup Time
(T
IS
min)
n/a
n/a
11.7
11.7
11.7
4
4
n/a
4
n/a
6
4
4
n/a
n/a
4
n/a
n/a
4
4
n/a
6
n/a
n/a
n/a
4
n/a
n/a
Hold Time
(T
IH
min)
n/a
n/a
0.5
0.5
0.5
1
1
n/a
1
n/a
1
1
1
n/a
n/a
1
n/a
n/a
1
1
n/a
1
n/a
n/a
n/a
1
n/a
n/a
Output (ns)
Valid Delay
(T
OV
max)
10
10
n/a
10
10
7.2
6.5
6.5
7.2
6.5
n/a
6.5
6.5
6.5
6.5
n/a
6.0
6.5
n/a
n/a
n/a
n/a
6.5
6.5
6.5
n/a
6.5
6.5
Hold Time
(T
OH
min)
1
1
n/a
1
1
1.5
1.5
1.5
1.5
1.5
n/a
1.5
1.5
1.5
1.5
n/a
1.5
1.5
n/a
n/a
n/a
n/a
1.5
1.5
1.5
n/a
1.5
1.5
Output Current (mA)
I/O H
(minimum)
5.1
15.3
na
5.1
15.3
15.3
15.3
10.3
15.3
15.3
15.3
15.3
15.3
7.1
7.1
n/a
15.3
7.1
na
na
15.3
10.3
5.1
10.3
5.1
na
5.1
5.1
I/O L
(minimum)
6.8
10.2
na
6.8
10.2
10.2
10.2
7.1
10.2
10.2
10.2
10.2
10.2
9.6
9.6
n/a
10.2
9.6
na
na
10.2
7.1
6.8
7.1
6.8
na
6.8
6.8
PLB Clk
PerClk
1
Clock
Notes
External Slave Peripheral Interface
DMAAck0:1
DMAAck2:3
DMAReq0:3
EOT0:1/TC0:1
EOT2:3/TC2:3
PerAddr02:31
PerBLast
PerCS0:5
PerData00:15
PerOE
PerReady
PerR/W
PerWBE0:1
BusReq
ExtAck
ExtReq
ExtReset
HoldAck
HoldReq
HoldPri
PerClk
PerErr
NAND Flash Interface
NFALE
NFCE0:3
NFCLE
NFRdyBusy
NFREn
NFWEn
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
External Master Peripheral Interface
70
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
