Revision 1.26 – April 25, 2007
440EP – PPC440EP Embedded Processor
Data Sheet
Figure 10. DDR SDRAM Read Data Path
Package pins
Mux
D
RDSP
Q
Stage 1
D
Stage 2
Q
D
Q
D
Stage 3
Q
ECC
FF
PLB bus
Data
FF,
XL
C
FF
FF
C
C
C
DQS
1/4
Cycle
Delay
PLB Clock
Programmed
Read Clock
Delay
Read Select
(SDRAM0_TR1)
FF Timing:
T
IS
= Input setup time = 0.2ns
T
IH
= Input hold time = 0.1ns
T
P
= Propagation delay (D to Q or C to Q) = 0.4ns maximum
FF: Flip-Flop
XL: Transparent Latch
Table 22. I/O Timing—DDR SDRAM T
SIN
and T
DIN
Notes:
1. T
SIN
= Delay from DQS at package pin to C on Stage 1 FF.
2. T
DIN
= Delay from data at package pin to D on Stage 1 FF.
3. Clock speed for the values in the table is 133MHz.
4. The time values for T
SIN
include 1/4 of a cycle at 133MHz (7.5ns x 0.25 = 1.875 ns).
Signal Name
DQS0
DQS1
DQS2
DQS3
DQS8
T
SIN
(ns)
minimum
2.74
2.75
2.74
2.76
2.77
T
SIN
(ns)
maximum
3.70
3.69
3.69
3.69
3.68
Signal Name
MemData00:07
MemData08:15
MemData16:23
MemData24:31
ECC0:7
T
DIN
(ns)
minimum
0.86
0.87
0.89
0.88
0.89
T
DIN
(ns)
maximum
1.87
1.86
1.86
1.85
1.83
In the following examples, the data strobes (DQS) and the data are shown to be coincident. There is actually a
slight skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal
routing. It is recommended that the signal length for all of the eight DQS signals be matched.
76
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