440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
PPC440GP Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
Timers
MMU
Power
Mgmt
DCRs
PPC440
45 internal
13 external
Processor Core
JTAG
32KB
D-Cache
Trace
32KB
I-Cache
Arb
DCR Bus
GP
Timers
GPIO
IIC
x2
UART
x2
On-chip Peripheral Bus (OPB)
SRAM
8KB
DMA
Controller
(4-Channel)
OPB
Bridge
Processor Local Bus (PLB)
Ethernet
x2
External
External
Bus Master
Bus
Controller
Controller
66MHz max
32-bit addr
32-bit data
MAL
DDR SDRAM
Controller
133MHz max
13-bit addr
32/64-bit data
PCI-X
Bridge
1 MII
or
2 RMII
133MHz max
The PPC440GP is designed using the IBM
®
Microelectronics Blue Logic
™
methodology in which major functional
blocks are integrated together to create an application-specific product (ASIC). This approach provides a
consistent way to create complex ASICs using IBM CoreConnect Bus
™
Architecture.
Note:
IBM CoreConnect buses provide:
• 128-bit PLB interfaces up to 133.33MHz
• 32-bit OPB interfaces up to 66.66MHz, 266MB/s
Address Maps
The PPC440GP incorporates two address maps. The first is a fixed processor system memory address map. This
address map defines the possible contents of various address regions which the processor can access. The
second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running
on the PPC440GP processor through the use of
mtdcr
and
mfdcr
instructions.
6
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
