Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
I/O Specifications—All Speeds (Sheet 3 of 4)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and
1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
3. The clock frequency for RMII operation is 50MHz 100ppm.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
Internal Peripheral Interface
IICxSClk
na
na
na
na
na
na
15.3
15.3
na
10.2
10.2
na
IICxSDA
UARTSerClk
UART0_Rx
UART0_Tx
UART0_DCD
UART0_DSR
UART0_CTS
UART0_DTR
UART0_RI
UART0_RTS
UART1_Rx
UART1_Tx
UART1_DSR/CTS
UART1_RTS/DTR
Interrupts Interface
IRQ00:12
na
na
na
na
na
na
na
na
10.3
na
7.1
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
10.3
na
7.1
na
na
na
na
na
na
na
10.3
na
7.1
na
10.3
na
7.1
na
10.3
7.1
na
na
JTAG Interface
TDI
na
na
na
na
async
async
async
async
async
TMS
TDO
15.3
na
10.2
na
TCK
TRST
na
na
AMCC
67
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
