PPC440SP-AFC533C 参数 Datasheet PDF下载

Revision 1.23 - Sept 26, 2006

Data Sheet

PPC440SP Functional Block Diagram

Figure 2. PPC440SP Functional Block Diagram

Clock,

Control,

Reset

Universal

Interrupt

Controller

Timers

MMU

DCRs

Power

Mgmt

UART2

IIC1

DCR Bus

GPT

GPIO

IIC0

UART1

UART0

PPC440

Processor Core

JTAG

32KB

D-Cache

Trace

32KB

I-Cache

On-chip Peripheral Bus (OPB)

L2 Cache/SRAM

OPB

Bridge

PLB

Processor Local Bus (PLB)

Arbiter

MAL

Ethernet

10/100/

1000

(EMAC)

MII,

GMII

External

Bus Controller

(EBC)

Low Latency (LL) Segment

High Bandwidth (HB) Segment

I2O/DMA

Controller

(DMA0 and

DMA1)

Memory

Queue

DDR2 SDRAM

Controller

XOR/DMA

Accelerator

Unit

(DMA2)

DDR PCI-X

PCI2

PCI0 PCI1

Host

Local Local

64 bits 64 bits 32 bits

The PPC440SP is a System on a chip, which uses IBM

®

CoreConnect Bus™ Architecture.

Implemented with the Crossbar option, the IBM CoreConnect buses provide:

• 128-bit Data, 64-bit Address PLB interfaces up to 166.66MHz, 2.6GB/s on both the Read and Write data

paths (10.6GB/sec total)

• 32-bit OPB interfaces up to 83.33MHz, 333MB/s

Address Maps

The PPC440SP incorporates two address maps. The first is a fixed processor system memory address map. This

address map defines the possible contents of various processor accessible address regions. The second address

map identifies the system Device Configuration Registers (DCRs). DCRs are accessed by software running on the

PPC440SP processor through the use of

mtdcr

and

mfdcr

instructions.

AMCC Proprietary

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