PPC440SPE-AGB533C 参数 Datasheet PDF下载

Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

I/O Specifications

Table 13. Peripheral Interface Clock Timings

Parameter

PCIX0Clk input frequency (asynchronous mode)

PCIX0Clk period (asynchronous mode)

PCIX0Clk input high time

PCIX0Clk input low time

EMCMDClk output frequency

EMCMDClk period

EMCMDClk output high time

EMCMDClk output low time

EMCTxClk input frequency

EMCTxClk period

EMCTxClk input high time

EMCTxClk input low time

EMCRxClk input frequency

EMCRxClk period

EMCRxClk input high time

EMCRxClk input low time

PerClk output frequency (for sync. slaves)

PerClk period

PerClk output high time

PerClk output low time

UARTSerClk input frequency

UARTSerClk period

UARTSerClk input high time

UARTSerClk input low time

TmrClk input frequency

TmrClk period

TmrClk input high time

TmrClk input low time

Notes:

1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at an integral divisor ratio of the frequency of

the PLB clock. The maximum OPB clock frequency is 83.33 MHz. Refer to the Clocking chapter of the

PPC440SPe

Embedded Processor User’s Manual

for details.

2. When the PCI-X interface is used to support a legacy PCI interface, the maximum PCIXClk frequency is 66.66MHz.

Min

–

7.5

40% of nominal period

40% of nominal period

–

400

160

160

2.5

40

35% of nominal period

35% of nominal period

2.5

40

35% of nominal period

35% of nominal period

–

12

50% of nominal period

33% of nominal period

–

2TOPB+2

TOPB+1

TOPB+1

–

10

40% of nominal period

40% of nominal period

Max

133.33

–

60% of nominal period

60% of nominal period

2.5

–

–

–

25

400

–

–

25

400

–

–

83.33

–

66% of nominal period

50% of nominal period

1000/(2TOPB

1

+2ns)

–

–

–

100

–

60% of nominal period

60% of nominal period

Units

MHz

ns

ns

ns

MHz

ns

ns

ns

MHz

ns

ns

ns

MHz

ns

ns

ns

MHz

ns

ns

ns

MHz

ns

ns

ns

MHz

ns

ns

ns

1

1

1

1

Notes

2

AMCC Proprietary

65