Table 3.
Am29F010 Autoselect Codes (High Voltage Method)
A16
to
A14
X
X
A13
to
A10
X
X
A8
to
A7
X
X
A5
to
A2
X
X
DQ7
to
DQ0
01h
20h
01h
(protected)
Description
Manufacturer ID: AMD
Device ID: Am29F010
CE#
L
L
OE#
L
L
WE#
H
H
A9
V
ID
V
ID
A6
L
L
A1
L
L
A0
L
H
Sector Protection Verification
L
L
H
SA
X
V
ID
X
L
X
H
L
00h
(unprotected)
L = Logic Low = V
IL
, H = Logic High = V
IH
, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The
hardware sector unprotection feature re-enables
both program and erase operations in previously pro-
tected sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure re-
quires a high voltage (V
ID
) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, publication number 20495. Contact an
AMD representative to obtain a copy of the appropriate
document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
gramming, which might otherwise be caused by spuri-
ous system level signals during V
CC
power-up and
power-down transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when V
CC
is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE#
= V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write cy-
cle, CE# and WE# must be a logical zero while OE#
is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power
up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
a u to m at i c a l l y r e s e t t o r e a d i n g a r r a y d a ta o n
power-up.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
Am29F010
9
AMD [ ADVANCED MICRO DEVICES ]
