DATA SHEET
AC CHARACTERISTICS
t
RC
Addresses
VA
t
ACC
t
CE
CE#
t
CH
OE#
t
OEH
WE#
t
OH
DQ7
High Z
VA
VA
t
OE
t
DF
Complement
Complement
True
Valid Data
High Z
DQ0–DQ6
t
BUSY
RY/BY#
Status Data
Status Data
True
Valid Data
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 15.
Data# Polling Timings (During Embedded Algorithms)
t
RC
Addresses
VA
t
ACC
t
CE
CE#
t
CH
OE#
t
OEH
WE#
t
OH
DQ6/DQ2
t
BUSY
RY/BY#
High Z
VA
VA
VA
t
OE
t
DF
Valid Status
(first read)
Valid Status
(second read)
Valid Status
(stops toggling)
Valid Data
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
Figure 16.
Toggle Bit Timings (During Embedded Algorithms)
November 2, 2006 21504E5
Am29F800B
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AMD [ ADVANCED MICRO DEVICES ]
