PRELIMINARY
Am53C94/Am53C96
High Performance SCSI Controller
DISTINCTIVE CHARACTERISTICS
s
s
s
s
s
s
s
s
s
Pin/function compatible with NCR53C94/53C96
AMD’s Patented GLITCH EATER
TM
Circuitry on
REQ
and
ACK
inputs
5 Mbytes per second synchronous SCSI
transfer rate
20 Mbytes per second DMA transfer rate
16-bit DMA Interface plus 2 bits of parity
Flexible three bus architecture
Single ended SCSI bus supported by
Am53C94
Single ended and differential SCSI bus
supported by Am53C96
Selection of multiplexed or non-multiplexed
address and data bus
s
s
s
s
s
s
s
s
Advanced
Micro
Devices
High current drivers (48 mA) for direct
connection to the single ended SCSI bus
Supports Disconnect and Reselect commands
Supports burst mode DMA operation with a
threshold of 8
Supports 3-byte-tagged queuing as per the
SCSI-2 specification
Supports group 2 and 5 command recognition
as per the SCSI-2 specification
Advanced CMOS process for low power
consumption
Am53C94 available in 84-pin PLCC package
Am53C96 available in 100-pin PQFP package
GENERAL DESCRIPTION
The High Performance SCSI Controller (HPSC) has a
flexible three bus architecture. The HPSC has a 16-bit
DMA interface, an 8 bit host data interface and an 8-bit
SCSI data interface. The HPSC is designed to minimize
host intervention by implementing common SCSI se-
quences in hardware. An on-chip state machine re-
duces protocol overheads by performing the required
sequences in response to a single command from the
host. Selection, reselection, information transfer and
disconnection commands are directly supported.
The 16-byte-internal FIFO further assists in minimizing
host involvement. The FIFO provides a temporary stor-
age for all command, data, status and message bytes as
they are transferred between the 16 bit host data bus
and the 8 bit SCSI data bus. During DMA operations the
FIFO acts as a buffer to allow greater latency in the DMA
channel. This permits the DMA channel to be sus-
pended for higher priority operations such as DRAM re-
fresh or reception of an ISDN packet.
Parity on the DMA bus is optional. Parity can either be
generated and checked or it can be simply passed
through.
The patented GLITCH EATER Circuitry in the High Per-
formance SCSI Controller detects signal changes that
are less than or equal to 15 ns and filters them out. It is
designed to dramatically increase system performance
and reliability by detecting and filtering glitches that can
cause system failure.
The GLITCH EATER Circuitry is implemented on the
ACK
and
REQ
lines only. These lines often encounter
many electrical anomalies which degrade system per-
formance and reliability. The two most common are Re-
flections and Voltage Spikes. Reflections are a result of
high current SCSI signals that are mismatched by stubs,
cables and terminators. These reflections vary from ap-
plication to application and can trigger false handshake
signals on the
ACK
and
REQ
lines if the voltage ampli-
tude is at the TTL threshold levels. Spikes are generated
by high current SCSI signals switching concurrently. On
the control signals (ACK and
REQ)
they can trigger false
data transfers which result in loss of data, addition of
random data, double clocking and reduced system reli-
ability. AMD’s GLITCH EATER Circuitry helps maintain
excellent system performance by treating the glitches.
Refer to the diagram on the next page.
This document contains information on a product under development at Advanced Micro Devices Inc. The information is intended
to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication#
16506
Rev.
C
Issue Date:
May 1993
Amendment
/0
AMD [ ADVANCED MICRO DEVICES ]
