SWITCHING WAVEFORMS
E1 to DET
E1
DET
tgkde
tshde
tgkde
tshde
E0 to DET
E1
E0
DET
tshdd
Note:
All delays measured at 1.4 V level.
tshd0
tgkdd
tgkd0
Notes:
1. Unless otherwise noted, test conditions are V
CC
= +5 V, V
EE
= –5 V, C
HP
= 0.33
µF,
R
DC1
= R
DC2
= 9.26
kΩ,
C
DC
= 0.33
µF,
R
D
= 35.4
kΩ,
C
CAS
= 0.33
µF,
no fuse resistors, BAT = –48 V, R
L
= 900
Ω,
and R
TMG
= 1700
Ω.
2. a. Overload level is defined when THD = 1%.
b. Overload level is defined when THD = 1.5%
3. Balance return signal is the signal generated at V
TX
by V
RX
. This specification assumes the two-wire AC load impedance
matches the programmed impedance.
4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
5. This parameter is tested at 1 kHz with a termination impedance of 900
Ω
and an R
L
of 600
Ω
in production. Performance at
other frequencies is guaranteed by characterization.
6. Tested with 0
Ω
source impedance. 2 MΩ is specified for system design only.
7. Assumes the following Z
T
networks:
(900
Ω):
VTX
90 kΩ
90 kΩ
150 pF
RSN
(600
Ω):
VTX
60 kΩ
60 kΩ
150 pF
RSN
8. Group delay can be considerably reduced by using a Z
T
network such as that shown in Note 7 above. The network reduces
the group delay to less than 2
µs.
The effect of group delay on the linecard performance may be compensated for by using
the QSLAC™ or DSLAC™ device.
10
Am7945 Data Sheet
AMD [ ADVANCED MICRO DEVICES ]
