PRELIMINARY
Am79C960
PCnet
TM
-ISA Single-Chip Ethernet Controller
DISTINCTIVE CHARACTERISTICS
s
Single-chip Ethernet controller for the Industry
Standard Architecture (ISA) and Extended
Industry Standard Architecture (EISA) buses
s
Supports IEEE 802.3/ANSI 8802-3 and Ethernet
standards
s
Direct interface to the ISA or EISA bus
s
Software compatible with AMD’s Am7990
LANCE register and descriptor architecture
s
Low power, CMOS design with sleep mode
allows reduced power consumption for critical
battery powered applications
s
Individual 136-byte transmit and 128-byte
receive FIFOs provide packet buffering for
increased system latency, and support the
following features:
— Automatic retransmission with no FIFO
reload
— Automatic receive stripping and transmit
padding (individually programmable)
— Automatic runt packet rejection
— Automatic deletion of received collision
frames
s
Dynamic transmit FCS generation program-
mable on a frame-by-frame basis
s
Single +5 V power supply
s
Internal/external loopback capabilities
s
Supports optional Boot PROM for diskless
node applications
Advanced
Micro
Devices
s
Provides integrated Attachment Unit Interface
(AUI) and 10BASE-T transceiver with 3 modes
of port selection:
— Automatic selection of AUI or 10BASE-T
— Software selection of AUI or 10BASE-T
— Jumper selection of AUI or 10BASE-T
s
Automatic Twisted Pair receive polarity
detection and automatic correction of the
receive polarity
s
Supports bus-master and shared-memory
architectures to fit in any PC application
s
Supports edge and level-sensitive interrupts
s
DMA Buffer Management Unit for reduced CPU
intervention
s
Integral DMA controller allows higher
throughput by by-passing the platform DMA
s
JTAG Boundary Scan (IEEE 1149.1) test access
port interface for board level production test
s
Integrated Manchester Encoder/Decoder
s
Supports the following types of network
interfaces:
— AUI to external 10BASE2, 10BASE5,
10BASE-T or 10BASE-F MAU
— Internal 10BASE-T transceiver with Smart
Squelch to Twisted Pair medium
s
Supports LANCE General Purpose Serial
Interface (GPSI)
s
120-pin PQFP package
GENERAL DESCRIPTION
The PCnet-ISA controller, a single-chip Ethernet con-
troller, is a highly integrated system solution for the
PC-AT Industry Standard Architecture (ISA ) architec-
ture. It is designed to provide flexibility and compatibility
with any existing PC application. This highly integrated
120-pin VLSI device is specifically designed to reduce
parts count and cost, and addresses applications where
higher system throughput is desired. The PCnet-ISA
controller is fabricated with AMD’s advanced low-power
CMOS process to provide low stand by current for
power sensitive applications.
The PCnet-ISA controller is a DMA-based device with a
dual architecture that can be configured in two different
Publication#
16907
Rev.
B
Issue Date:
May 1994
Amendment
/0
operating modes to suit a particular PC application. In
the Bus Master Mode all transfers are performed using
the integrated DMA controller. This configuration en-
hances system performance by allowing the PCnet-ISA
controller to bypass the platform DMA controller and di-
rectly address the full 24-bit memory space. The
implementation of Bus Master Mode allows minimum
parts count for the majority of PC applications. The
PCnet-ISA controller can be configured to perform
Shared Memory operations for compatibility with low-
end machines, such as PC/XTs that do not support Bus
Master and high-end machines that require local packet
buffering for increased system latency.
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This document contains information on a product under development at Advanced Micro Devices, Inc.
The information is intended to help you to evaluate this product. AMD reserves the right to change or
discontinue work on this proposed product without notice.
AMD [ ADVANCED MICRO DEVICES ]
