Am79C961A
PCnet
™
-ISA II Jumperless, Full Duplex Single-Chip
Ethernet Controller for ISA
DISTINCTIVE CHARACTERISTICS
s
Single-chip Ethernet controller for the Industry
Standard Architecture (ISA) and Extended
Industry Standard Architecture (EISA) buses
s
Supports IEEE 802.3/ANSI 8802-3 and Ethernet
standards
s
Supports full duplex operation on the
10BASE-T, AUI, and GPSI ports
s
Direct interface to the ISA or EISA bus
s
Pin compatible to Am79C961 PCnet-ISA
+
Jumperless Single-Chip Ethernet Controller
s
Software compatible with AMD’s Am7990
LANCE register and descriptor architecture
s
Low power, CMOS design with sleep mode
allows reduced power consumption for critical
battery powered applications
s
Individual 136-byte transmit and 128-byte
receive FIFOs provide packet buffering for
increased system latency, and support the
following features:
— Automatic retransmission with no FIFO
reload
— Automatic receive stripping and transmit
padding (individually programmable)
— Automatic runt packet rejection
— Automatic deletion of received collision
frames
s
Dynamic transmit FCS generation
programmable on a frame-by-frame basis
s
Single +5 V power supply
s
Internal/external loopback capabilities
s
Supports 8K, 16K, 32K, and 64K Boot PROMs or
Flash for diskless node applications
s
Supports Microsoft’s Plug and Play System
configuration for jumperless designs
s
Supports staggered AT bus drive for reduced
noise and ground bounce
s
Integrated Magic Packet™ support for remote
wake up of Green PCs
s
Supports 8 interrupts on chip
s
Look Ahead Packet Processing (LAPP)
allows protocol analysis to begin before
end of receive frame
s
Supports 4 DMA channels on chip
s
Supports 16 I/O locations
s
Supports 16 boot PROM locations
s
Provides integrated Attachment Unit Interface
(AUI) and 10BASE-T transceiver with 2 modes of
port selection:
— Automatic selection of AUI or 10BASE-T
— Software selection of AUI or 10BASE-T
s
Automatic Twisted Pair receive polarity
detection and automatic correction of the
receive polarity
s
Supports bus-master, programmed I/O, and
shared-memory architectures to fit in any PC
application
s
Supports edge and level-sensitive interrupts
s
DMA Buffer Management Unit for reduced CPU
intervention which allows higher throughput by
by-passing the platform DMA
s
JTAG Boundary Scan (IEEE 1149.1) test access
port interface for board level production test
s
Integrated Manchester Encoder/Decoder
s
Supports the following types of network
interfaces:
— AUI to external 10BASE2, 10BASE5,
10BASE-T or 10BASE-F MAU
— Internal 10BASE-T transceiver with Smart
Squelch to Twisted Pair medium
s
Supports LANCE General Purpose Serial
Interface (GPSI)
s
132-pin PQFP and 144-pin TQFP packages
s
Supports Shared Memory and PIO modes
s
Supports PCMCIA mode (144-TQFP version
only)
s
Support for operation in industrial temperature
range (–40
°
C to +85
°
C) available in both
packages
Publication#
19364
Rev:
D
Amendment/0
Issue Date:
March 2000
AMD [ ADVANCED MICRO DEVICES ]
