AMD
PRELIMINARY
BLOCK DIAGRAM
DI±
CI±
DO±
Phase =
Locked
Loop
AUI
Port
RX
MUX
Manchester
Decoder
FIFO
Preamble
Jam Sequence
FIFO
Control
TX
MUX
RXD±
TXD±
TXP±
TP
Port
0
Manchester
Encoder
RXD±
TXD±
TXP±
TP
Port n
(Note)
bIMR
Chip
Control
Expansion Port
Partitioning
Link Test
RST
Reset
REQ
ACK
COL
DAT
JAM
X1
X2
SI
Clock
Gen
Timers
Test
and
Management
Port
SO
SCLK
TEST
CRS
STR
19406B-1
Note:
n=3 for Am79C982-4 and n=7 for Am79C982-8.
RELATED AMD PRODUCTS
Part No.
Am79C98
Am79C100
Am7996
Am79C981
Am79C987
Am79C940
Am79C90
Am79C900
Am79C960
Am79C961
Am79C965
Am79C970
Am79C974
Description
Twisted Pair Ethernet Transceiver (TPEX)
Twisted Pair Ethernet Transceiver Plus (TPEX+)
IEEE 802.3/Ethernet/Cheapernet Transceiver
Integrated Multiport Repeater Plus (IMR+)
Hardware Implemented Management Information Base™ (HIMIB™)
Media Access Controller for Ethernet (MACE™)
CMOS Local Area Network Controller for Ethernet (C-LANCE)
Integrated Local Area Communications Controller™ (ILACC™)
PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)
PCnet-ISA
+
Single-Chip Ethernet Controller for ISA (with Microsoft
®
Plug n’ Play
®
Support)
PCnet-32 Single-Chip 32-Bit Ethernet Controller
PCnet-PCI Single-Chip Ethernet Controller (for PCI bus)
PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems
1–4
Am79C982
AMD [ ADVANCED MICRO DEVICES ]
