F I N A L
word, or double word register operands to or from main
system memory. Multiple data transfers using the nor-
mal ADS and READY pins will occur if the operands
are misaligned relative to the effective address used.
The UMOV opcodes are 0F 10h, 0F 11h, 0F 12h, and
0F 13h. The UMOV instruction can use any of the 386
addressing modes, as specified in the ModR/M byte of
the opcode. Note that the 16- and 32-bit versions are
the same opcodes with the exception of the 66h oper-
and size prefix.
service routine normally returns to the instruction fol-
lowing the I/O instruction that caused the break. By
modifying the saved state instruction pointer, the rou-
tine can choose to return to the I/O instruction that
caused the break and re-execute that instruction. The
default is to return to the following instruction (except
for REP I/O string instruction). To re-execute the I/O in-
struction that caused the break, the SMI service routine
must copy the I/O instruction pointer over the default
pointer. This feature is particularly useful when an ap-
plication program requests an access to a peripheral
that has been powered down. The SMI service routine
can restore power to the peripheral and initiate a re-ex-
ecution sequence transparent to the application pro-
gram. This re-execution feature should only be used if
the SMI is in response to an I/O trap with IIBEN active.
Note that the I/O instruction break feature is not en-
abled for memory mapped I/O devices or for coproces-
sor bus cycles even if IIBEN is active.
I/O Instruction Break Timing
The I/O Instruction Break feature requires that SMI be
sampled active (Low) by the processor at least three
CLK2 edges before the CLK2 edge that ends the I/O
cycle with an active READY signal. This timing applies
for both pipelined and non-pipelined cycles. If this tim-
ing constraint is not met, additional instructions may be
executed by the internal execution unit prior to entering
SMM. Depending on the state of the prefetch queue at
the time the SMI is asserted, instruction fetch cycles
may occur on the normal ADS interface before the
SMM save state process begins with the assertion of
SMIADS. However, this fetched code will not be exe-
cuted.
I/O Instruction Break (Am386SXLV Only)
The Am386SXLV microprocessor has an I/O instruc-
tion break feature that allows the system logic to imple-
ment I/O trapping for peripheral devices. To enable the
I/O Instruction break feature, IIBEN must first be as-
serted active Low. On detecting an I/O instruction, the
processor prevents the execution unit from executing
further instructions until READY is driven active Low by
the system. Once READY is driven active, the execu-
tion unit either immediately responds to any active in-
terrupt request or continues executing instructions fol-
lowing the I/O instruction that caused the break.
The I/O instruction break feature can be used to allow
system logic to implement I/O trapping for peripheral
devices. On sensing an I/O instruction, the system
drives the SMI pin active before driving READY active.
This ensures that the interrupt service routine is exe-
cuted immediately following the I/O instruction that
caused the break. (If the I/O instruction break feature is
not enabled via IIBEN, several instructions could exe-
cute before the SMI service routine is executed.)
The SMI service routine can access the peripheral for
which SMI was asserted and modify its state.The SMI
6
Am386SX/SXL/SXLV Microprocessors Data Sheet
AMD [ ADVANCED MICRO DEVICES ]
