AME, Inc.
AME8500 / 8501
µ
Processor Supervisory
n
Timing Diagram
V
Release
V
TH
V
DD
T
D2
50%
RESET
T
D1
50%
T
D2
50%
RESETB
T
D1
50%
n
Applications Information
Supply Transients
These devices have a certain immunity to fast negative
going transients. In the following pages the graph titled
“Glitch Rejection” indicates the maximum allowable glitch
amplitude and duration to avoid triggering an unintended
reset. As shown in the graph shorter transients can have
larger amplitudes without triggering resets.
Glitch Rejection
140
120
220
Reset Time vs. Temperature
215
Glitch Duration (µS)
µ
Reset Time (mS)
100
80
60
40
20
0
0.01
0.1
1
210
205
AME8500AEETAF26
200
195
190
-45
-5
25
55
85
115
Glitch Amplitude (V)
Temperature
(
o
C)
10
AME [ ANALOG MICROELECTRONICS ]
