AME, Inc.
AME8550
Voltage Detector
n
Functional Description
(CMOS output without delay)
1. When input voltage (V
DD
) rises above detect voltage
(V
DF
), output voltage (V
OUT
) will be equal to V
DD
.
( A condition of high impedance exists with Nch open
drain output configurations. )
2. When input voltage (V
DD
) falls below detect voltage
(V
DF
), output voltage (V
OUT
) will be equal to the ground
voltage (V
SS
) level.
3. When input voltage (V
DD
) falls to a level below that of
the minimum operating voltage (V
MIN
), output will become
unstable. In this condition, V
DD
will equal the pulled-up
output ( should output be pulled-up.)
4. When input voltage (V
DD
) rises above the ground volt-
age (V
SS
) level, output will be unstable at levels below the
minimum operating voltage (V
MIN
). Between the V
MIN
and
detect release voltage (V
DR
) levels, theground voltage (V
SS
)
level will be maintained.
5. When input voltage (V
DD
) rises above detect release
voltage (V
DR
), output voltage (V
OUT
) will be equal to V
DD
.
( A condition of high impedance exists with Nch open
drain output configurations. )
6. The difference between V
DR
and V
DF
represents the
hysteresis range.
n
Functional Description
(CMOS output with delay)
1. When input voltage (V
DD
) rises above detect voltage
(V
DF
), output voltage (V
OUT
) will be equal to V
DD
.
( A condition of high impedance exists with Nch open
drain output configurations. )
2. When input voltage (V
DD
) falls below detect voltage
(V
DF
), output voltage (V
OUT
) will be equal to the ground
voltage (V
SS
) level.
3. When input voltage (V
DD
) falls to a level below that of
the minimum operating voltage (V
MIN
), output will become
unstable. In this condition, V
DD
will equal the pulled-up
output ( should output be pulled-up.)
4. When input voltage (V
DD
) rises above the ground volt-
age (V
SS
) level, output will be unstable at levels below the
minimum operating voltage (V
MIN
). Between the V
MIN
and
detect release voltage (V
DR
) levels, theground voltage (V
SS
)
level will be maintained.
5. When input voltage (V
DD
) rises above detect release
voltage (V
DR
), output voltage (V
OUT
) will be equal to V
DD
after T
D
delay time.
Q = V x C = I x T
D
VxC
T=
I
V=V
REF
V
REF
* 1nF
For Example, T
D
=
75nA
( A condition of high impedance exists with Nch open
drain output configurations. )
6. The difference between V
DR
and V
DF
represents the
hysteresis range.
n
Timing Chart
6
Input Voltage (V
DD
)
Detect Release Voltage (V
DR
)
Detect Voltage (V
DF
)
n
Timing Chart
6
Input Voltage (V
DD
)
Detect Release Voltage (V
DR
)
Detect Voltage (V
DF
)
Min. Operating Voltage (V
MIN
)
Ground Voltage (V
ss
)
Output Voltage (V
OUT
)
T
D
Min. Operating Voltage (V
MIN
)
Ground Voltage (V
ss
)
Output Voltage (V
OUT
)
Ground Voltage (V
ss
)
1
2
3
4
5
1
2
3
4
5
Ground Voltage (V
ss
)
13
AME [ ANALOG MICROELECTRONICS ]
