AME
High PSRR, Low Quiescent Current,
150mA Dual CMOS LDO
AME8755
n Pin Description
Pin Name
Pin Description
LDO voltage regulator output pin.
OUT1
IN
m
It should be decoupled with a 1 F or greater value low ESR ceramic capacitor.
Input voltage pin.
It should be decoupled with 1mF or greater capacitor.
LDO voltage regulator output pin.
It should be decoupled with a 1mF or greater value low ESR ceramic capacitor.
OUT2
Enable pin.
EN2
GND
EN1
When pulled low, the PMOS pass transistor turns off OUT2, current consuming
less than 1mA.
Ground connection pin.
Enable pin.
When pulled low, the PMOS pass transistor turns off OUT1, current consuming
m
less than 1 A.
4
Rev. A.01