AMIS-30623 LIN Microstepping Motordriver
16.3 Functional Description
16.3.1. Analog Part
Data Sheet
The transmitter is a low-side driver with a pull-up resistor and slope control.
Figure 5
shows the characteristics of the transmitted signal,
including the delay between internal TxD – and LIN signal. See
AC Parameters
for timing values.
The receiver mainly consists of a comparator with a threshold equal to Vbb/2.
Figure 5
also shows the delay between the received
signal and the internal RXD signal. See also
AC Parameters
for timing values.
16.3.2. Protocol Handler
This block implements:
•
bit synchronization
•
bit timing
•
the MAC layer
•
the LLC layer
•
the supervisor
16.3.3. Electro Magnetic Compatibility
EMC behavior fulfills requirements defined by LIN specification, rev. 1.3.
16.4 Error Status Register
The LIN interface implements a register containing an error status of the LIN communication. This register is as follows:
Table 30: LIN Error Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Not
used
Not
used
Not
used
With:
Not
used
Time
out
error
Data
error
Flag
Header
error
Flag
Bit
error
Flag
Time out error:
Data error flag = Checksum error + StopBit error + Length error
Header error flag
= Parity + SynchField error
Bit error flag :
A
GetFullStatus
frame will reset the error status register.
16.5 Physical Address of the Circuit
The circuit must be provided with a physical address in order to discriminate this circuit from other ones on the LIN bus. This address is
coded on 7 bits, yielding the theoretical possibility of 128 different circuits on the same bus. It is a combination of 4 OTP memory bits
and of the 3 hardwired address bits (pins HW[2:0]). However the maximum number of nodes in a LIN network is also limited by the
physical properties of the bus line. It is recommended to limit the number of nodes in a LIN network to not exceed 16. Otherwise the
reduced network impedance may prohibit a fault free communication under worst case conditions. Every additional node lowers the
network impedance by approximately 3%.
AD6 AD5 AD4 AD3 AD2 AD1 AD0
Physical address
↑
↑
↑
PA3 PA2 PA1 PA0 OTP memory
HW0 HW1 HW2
Hardwired bits
Note:
Pins HW0 and HW1 are 5V digital inputs, whereas pin HW2 is compliant with a 12V level, e.g. it can be connected to Vbat or Gnd via a terminal of the PCB. To provide
cleaning current for this terminal, the system used for pin SWI is also implemented for pin HW2 (see
Hardwired Address HW2).
AMI Semiconductor
– June 2006, Rev 3.0
43
www.amis.com
AMI [ AMI SEMICONDUCTOR ]
