AMIS-710600-A8: 600dpi CIS Module
Data Sheet
5.0 Timing Characteristics of the Module (25°C)
The input control clocks and video pixel output relationships are depicted in Figure 3. As indicated, the internal shift register is loaded
on the falling edges of the module's clock, CP and during this time the SP is high or true. To ensure that only one shift register pulse is
loaded into the shift register during any one line scan, only one SP is allowed to go high for one CP cycle going low. After loading the
shift register, the SP is to remain low throughout the remainder of the line scan; otherwise multiple start pulses will load into the shift
register. To prevent this phenomenon, as the timing diagram shows, SP should occur only once in one CP cycle. When only one pulse
is loaded in the register, a single pulse shifts down the register, accessing a single photo-site with each shift and sequentially reading it
out onto the common video line where the video pixel is amplified and produced at the output I/O.
Figure 3: Timing Diagram of SP Relative to First Pixel
The call outs for the switching characteristics in Figure 3 are given in Table 6. This table defines the symbols used in the timing diagram
and calls out their time durations.
Table 6: Timing Definition and Specifications
Item
Symbol
Clock cycle time
to
Clock pulse width
tw
Clock duty cycle
Prohibit crossing time of SP
tprh
Data setup time
tds
Data hold time
tdh
Signal delay time
tdl
Signal sample and hold time
tsh
Min.
290
71
25
30
30
30
50
120
Typ.
Max.
7440
75
Units
ns
ns
%
ns
ns
ns
ns
ns
AMI Semiconductor
– July. 06, M-20597-001
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