A29040A Series
The host system can detect whether a program or erase
operation is complete by reading the I/O
7
(
Data
Polling) and
I/O
6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data contents
of other sectors. The A29040A is fully erased when shipped
from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the sectors
of memory. This can be achieved via programming
equipment.
The Erase Suspend feature enables the user to put erase on
hold for any period of time to read data from, or program data
to, any other sector that is not selected for erasure. True
background erase can thus be achieved.
Power consumption is greatly reduced when the device is
placed in the standby mode.
Pin Configurations
n
DIP
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O
0
I/O
1
I/O
2
VSS
1
2
3
4
5
6
32
31
30
29
28
27
VCC
WE
A17
n
PLCC
VCC
A12
A16
A18
4
3
A15
2
1
32
31
A14
A13
A8
A9
A11
OE
A10
CE
I/O
7
I/O
6
I/O
5
I/O
4
A7
A6
A5
A4
A3
A2
A1
A0
I/O
0
5
6
7
8
9
10
11
12
13
30
A17
WE
29
28
27
26
A14
A13
A8
A9
A11
OE
A10
CE
I/O
7
7
8
9
10
11
12
13
14
15
16
A29040A
26
25
24
23
22
21
20
19
18
17
A29040AL
25
24
23
22
21
14
15
16
17
18
19
I/O
5
VSS
I/O
1
I/O
2
I/O
3
I/O
4
I/O
3
n
TSOP (Forward type)
A11
A9
A8
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
VSS
I/O
2
I/O
1
I/O
0
A0
A1
A2
A3
A29040AV
I/O
6
20
PRELIMINARY
(August, 2001, Version 0.1)
2
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
