A29L320A Series
erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two
write cycles to program data instead of four.
The host system can detect whether a program or erase
operation is complete by observing the RY /
BY
pin, or by
reading the I/O
7
(
Data
Polling) and I/O
6
(toggle) status bits.
After a program or erase cycle has been completed, the
device is ready to read array data or accept another
command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29L320A is fully erased
when shipped from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the
sectors of memory. This can be achieved via programming
equipment.
The Erase Suspend/Erase Resume feature enables the user
to put erase on hold for any period of time to read data from,
or program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware
RESET
pin terminates any operation in
progress and resets the internal state machine to reading
array data. The
RESET
pin may be tied to the system reset
circuitry. A system reset would thus also reset the device,
enabling the system microprocessor to read the boot-up
firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power
consumption is greatly reduced in both these modes.
Pin Configurations
TSOP (I)
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
RESET
NC
WP/ACC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
I/O
15
(A-1)
I/O
7
I/O
14
I/O
6
I/O
13
I/O
5
I/O
12
I/O
4
VCC
I/O
11
I/O
3
I/O
10
I/O
2
I/O
9
I/O
1
I/O
8
I/O
0
OE
VSS
CE
A0
A29L320AV
(November, 2007, Version 1.1)
2
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
