A43L2616B
cycle). The time required to complete the auto refresh
operation is specified by “tRC(min)”. The minimum number
of clock cycles required can be calculated by driving “tRC”
with clock cycle time and then rounding up to the next
higher integer. The auto refresh command must be
followed by NOP’s until the auto refresh operation is
completed. Both banks will be in the idle state at the end of
auto refresh operation. The auto refresh is the preferred
refresh mode when the SDRAM is being used for normal
data transactions. The auto refresh cycle can be performed
once in 15.6us or a burst of 4096 auto refresh cycles once
in 64ms.
Device Operations (continued)
Auto Precharge
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the
timing to satisfy tRAS(min) and “tRP” for the programmed
burst length and CAS latency. The auto precharge
command is issued at the same time as burst read or burst
write by asserting high on A10/AP. If burst read or burst
write command is issued with low on A10/AP, the bank is
left active until a new command is asserted. Once auto
precharge command is given, no new commands are
possible to that particular bank until the bank achieves idle
state.
Self Refresh
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and
all the input buffers except CKE. The refresh addressing
and timing is internally generated to reduce power
consumption.
Four Banks Precharge
Both banks can be precharged at the same time by using
Precharge all command. Asserting low on
,
and
CS RAS
with high on A10/AP after both banks have satisfied
WE
tRAS(min) requirement, performs precharge on both banks.
At the end of tRP after performing precharge all, both
banks are in idle state.
The self refresh mode is entered from all banks idle state
by asserting low on
,
,
and CKE with high
CS RAS CAS
on
. Once the self refresh mode is entered, only CKE
WE
Auto Refresh
state being low matters, all the other inputs including clock
are ignored to remain in the self refresh.
The storage cells of SDRAM need to be refreshed every
64ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal
counter increments automatically on every auto refresh
cycle to refresh all the rows. An auto refresh command is
The self refresh is exited by restarting the external clock
and then asserting high on CKE. This must be followed by
NOP’s for a minimum time of “tRC” before the SDRAM
reaches idle state to begin normal operation. If the system
uses burst auto refresh during normal operation, it is
recommended to used burst 4096 auto refresh cycles
immediately after exiting self refresh.
issued by asserting low on
,
and
with high
CS RAS
CAS
on CKE and
. The auto refresh command can only be
WE
asserted with both banks being in idle state and the device
is not in power down mode (CKE is high in the previous
(December, 2009, Version 1.3)
13
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
