A62L256 Series
Timing Waveforms (continued)
Read Cycle 3
(1, 3, 4)
CE
t
ACE
t
CLZ 5
t
CHZ 5
D
OUT
Notes: 1.
2.
3.
4.
5.
WE is high for Read Cycle.
Device is continuously enabled, CE = V
IL
.
Address valid prior to or coincident with CE transition low.
OE = V
IL
.
Transition is measured
±500mV
from steady state. This parameter is sampled and not 100% tested.
(6)
Write Cycle 1
(Write Enable Controlled)
t
WC
Address
t
AW
t
CW5
CE
(4)
t
WR 3
t
AS1
t
WP 2
WE
t
DW
t
DH
D
IN
t
WHZ 7
t
OW 7
D
OUT
PRELIMINARY
(November, 2001, Version 1.4)
8
AMIC Technology, Inc.