A63L8336
Timing Waveforms (continued)
tKC
CLK
ADSP
t
KH
tKL
tADSS
tADSH
ADSC
t
AS
t
AH
A1
A2
A3
A4
A5
A6
ADDRESS
tWS
tWH
GW,BWE,
BW1-BW4
(NOTE *3)
tCES
tCEH
CE
(NOTE *2)
ADV
OE
t
DS
tDH
tOELZ
tKQ
High-Z
High-Z
D(A3)
D(A6)
DIN
D(A5)
t
KQLZ
t
OEHZ
t
KQ
(NOTE *1)
Q(A4)
DOUT
Q(A4+3)
Q(A1)
Back-to-Back READs
Q(A2)
Q(A3)
Q(A4+1)
Q(A4+2)
Back-to-Back
WRITEs
Pass-through
READ
Single WRITE
BURST READ
(NOTE *4)
Read/Write Timing
Notes:
*1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the internal burst address immediately
following A4.
*2. Timing for CE2 and CE2 is identical to that for CE . As shown in this diagram, when CE is LOW, CE2 is
LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
*3. Byte Write enables are decided by means of a Write truth table.
*4. Pass-through occurs when data is first written, then Read in sequence.
PRELIMINARY
(July, 2005, Version 0.0)
13
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
