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A67L7336 参数 Datasheet PDF下载

A67L7336图片预览
型号: A67L7336
PDF下载: 下载PDF文件 查看货源
内容描述: 256K X 16/18 , 128K X 32/36 LVTTL ,流水线DBA SRAM [256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM]
分类和应用: 静态存储器
文件页数/大小: 19 页 / 275 K
品牌: AMICC [ AMIC TECHNOLOGY ]
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A67L8316/A67L8318/
A67L7332/A67L7336 Series
Pin Description (continued)
Pin No.
LQFP (X16/X18)
87
LQFP (X32/X36)
87
CEN
Symbol
Description
Synchronous Clock Enable : This active low input permits
CLK to propagate throughout the device. When HIGH, the
device ignores the CLK input and effectively internally
extends the previous CLK cycle. This input must meet setup
and hold times around the rising edge of CLK.
Snooze Enable : This active high asynchronous input
causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When active,
all other inputs are ignored.
Read/Write : This active input determines the cycle type
when ADV/ LD is LOW. This is the only means for
determining READs and WRITEs. READ cycles may not be
converted into WRITEs (and vice versa) other than by
loading a new address. A LOW on this pin permits BYTE
WRITE operations and must meet the setup and hold times
around the rising edge of CLK. Full bus width WRITEs
occur if all byte write enables are LOW.
SRAM Data I/O : Byte “a” is I/Oa pins; Byte “b” is I/Ob pins;
Byte “c” is I/Oc pins; Byte “d” is I/Od pins. Input data must
meet setup and hold times around CLK rising edge.
64
64
ZZ
88
88
R/
W
(a) 58, 59, 62, 63,
68, 69, 72, 73
(b) 8,9,12,13, 18,
19, 22,23
(a) 52, 53, 56, 57,
58, 59, 62, 63
(b) 68, 69, 72, 73,
74, 75, 78, 79
(c) 2, 3, 6, 7, 8, 9,
12, 13,
(d) 18, 19, 22, 23,
24, 25, 28, 29
51
80
1
30
31
I/Oa
I/Ob
I/Oc
I/Od
74
24
NC/I/Oa
NC/I/Ob
NC/I/Oc
NC/I/Od
MODE
No Connect/Data Bits : On the X16/32 version, these pins
are no connect (NC) and can be left floating or connected to
GND to minimize thermal impedance. On the X18/36
version, these bits are I/Os.
Mode : This input selects the burst sequence. A LOW on
this pin selects linear burst. NC or HIGH on this pin selects
interleaved burst. Do not alter input state while device is
operating.
No Connect : These pins can be left floating or connected to
GND to minimize thermal impedance.
31
1, 2, 3, 6, 7, 25,
28, 29, 30, 38, 39,
42, 43, 51, 52, 53,
56, 57, 75, 78, 79,
83, 84, 95, 96
38,39,42,43
83,84
NC
PRELIMINARY
(December, 1999, Version 0.1)
6
AMIC Technology, Inc.