A67L06181/A67L93361
Truth Table (Notes 5 - 7)
Operation
Address
Used
None
CE
CE2
CE2
ZZ
Deselected Cycle,
H
X
X
L
X
X
X
L
L
→
H
High-Z
Power-down
Deselected Cycle,
None
X
H
X
L
L
X
X
X
L
L
→
H
High-Z
Power-down
Deselected Cycle,
None
X
X
L
L
L
X
X
X
L
L
→
H
High-Z
Power-down
Continue Deselect
None
X
X
X
L
H
X
X
X
L
L
→
H
High-Z
1
Cycle
READ Cycle
External
L
L
H
L
L
H
X
L
L
L
→
H
Q
(Begin Burst)
READ Cycle
Next
X
X
X
L
H
X
X
L
L
L
→
H
Q
1,7
(Continue Burst)
NOP/Dummy READ
External
L
L
H
L
L
H
X
H
L
L
→
H
High-Z
2
(Begin Burst)
Dummy READ
Next
X
X
X
L
H
X
X
H
L
L
→
H
High-Z
1,2,7
(Continue Burst)
WRITE Cycle
External
L
L
H
L
L
L
L
X
L
L
→
H
D
3
(Begin Burst)
WRITE Cycle
Next
X
X
X
L
H
X
L
X
L
L
→
H
D
1,3,7
(Continue Burst)
NOP/WRITE Abort
None
L
L
H
L
L
L
H
X
L
L
→
H
High-Z
2,3
(Begin Burst)
WRITE Abort
Next
X
X
X
L
H
X
H
X
L
L
→
H
High-Z 1,2,3,7
(Continue Burst)
IGNORE Clock Edge
Current
X
X
X
L
X
X
X
X
H
L
→
H
-
4
(Stall)
SLEEP Mode
None
X
X
X
H
X
X
X
X
X
X
High-Z
Notes:
1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or
WRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is
executed first.
2. Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation. A WRITE
Abort means a WRITE command is given, but no operation is performed.
3. OE may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the
output drivers during a WRITE cycle. Some users may use OE when the bus turn-on and turn-off times do not meet their
requirements.
4. If an Ignore Clock Edge command occurs during a READ operation, the I/O bus will remain active (Low-Z). If it occurs
during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the Ignored Clock
Edge cycle.
5. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
BWx
= H means all byte write signals (
BW1
,
BW2
,
BW3
and
BW4
) are HIGH.
BWx
= L means one or more byte write signals are LOW.
6.
BW1
enables WRITEs to Byte “a” (I/Oa pins);
BW2
enables WRITEs to Byte “b” (I/Ob pins);
BW3
enables WRITEs to
Byte “c” (I/Oc pins);
BW4
enables WRITEs to Byte “d” (I/Od pins).
7. The address counter is incremented for all Continue Burst cycles.
ADV/
LD
L
R/
W
BWx
OE
CEN
CLK
I/O
Notes
PRELIMINARY
(August, 2005, Version 0.0)
8
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
