LP61L1008 Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
t
WC
Address
t
AW
t
CW5
CE
t
AS1
(4)
t
WR3
t
CW5
t
WP2
WE
t
DW
D
IN
t
DH
t
WHZ7
D
OUT
Notes: 1. t
AS
is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (t
WP
) of a low CE and a low WE .
3. t
WR
is measured from the earliest of CE or WE going high to the end of the Write cycle.
4. If the CE low transition with the WE low transition or after the WE transition, outputs remain in a high
impedance state.
5. t
CW
is measured from the later of CE going low to the end of Write.
6. OE is continuously low. ( OE = V
IL
)
7. Transition is measured
±500mV
from steady state. This parameter is sampled and not 100% tested.
(June, 2001, Version 2.0)
8
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
