LP621024D Series
Block Diagram
A0
VCC
GND
ROW
512 X 2048
A14
A15
A16
DECODER
MEMORY ARRAY
I/O1
COLUMN I/O
INPUT DATA
CIRCUIT
I/O8
CE2
CE1
OE
CONTROL
CIRCUIT
WE
Pin Descriptions - DIP/SOP
Pin Description - TSOP/TSSOP
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1
NC
No Connection
1 - 4, 7,
10 - 20, 31
A0 - A16
Address Inputs
Write Enable
2 - 12, 23,
25 - 28, 31
A0 - A16
Address Inputs
5
WE
CE2
VCC
NC
13 - 15,
17 - 21
6
8
9
Chip Enable
I/O1 - I/O8
Data Input/Outputs
Power Supply
No Connection
16
22
GND
CE1
OE
Ground
Chip Enable
21 - 23,
25 - 29
I/O1 - I/O8
Data Input/Outputs
24
29
Output Enable
Write Enable
24
30
GND
CE1
OE
Ground
WE
CE2
VCC
Chip Enable
30
32
Chip Enable
32
Output Enable
Power Supply (+5V)
(August, 2001, Version 1.0)
2
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
